Senior Project Associate and 1 Other Post in SLIET via Direct Recruitment
Event Status : Created Event
Timeline
Important Dates
Application Closing Date | 13/10/2023 |
Application Opening Date | 04/10/2023 |
Other Important Information
Appointment Type | Direct Recruitment |
Application Submission Method | Online |
Age Limit | 18-40 |
Qualification Required | Graduate, Doctorate |
Total Vacancies | 3 |
Advertisement Number | C2S/ECE/0011 |
Location of Posting/Admission | Sangrur District, Punjab, India, 148021 |
Exam | CSIR NET, GATE, UGC NET |
Salary | 42000, 31000, 25000 |
Age Relaxation Type | SC/ST, Other Backward Class, Woman, Person with Benchmark Disabilities |
Interview | Yes |
Work Experience | Yes |
Place of Posting/Admission | Longowal, Punjab, India |
Organisation Type | Educational Institution |
Website | http://sliet.ac.in/ |
Note: This information is common for all posts. For details on specific posts, refer to the official notification.
Posts Released
Important Updates
Refer to the official notification for more details.
Application Summary
Sant Longowal Institute of Engineering and Technology invites applications for the following posts via direct recruitment:
Post Name: Senior Project Associate
Essential Qualification:
1. Bachelor degree in engineering Or technology from recognised university or equivalent.
2. Four years experience in research and development in industrial and Academy, institution or science and technology organisations and scientific activities and services. Or
3. Doctoral degree in engineering from recognised university or equivalent
Desirable: Candidate having Ph.D in VLSI Design or Electronics & Communication Engineering or related discipline / 4 years of experience in VLSI Design and research paper publications in reputed journals.
Post Name: Project Associate-I
Essential Qualification: Bachelors degree in Engineering/Technology in Electronics and Communication or Electrical and Electronics Engineering or other relevant discipline with a minimum of 60% aggregate marks (or) CGPA of 6.5/10 in UG or PG for OC/OBC category candidates and 55% aggregate marks or equivalent CGPA of 6.0 for SC/ST candidates.
Desirable: Candidates having Master’s degree in Engineering/Technology in the fields of Electronics and Communication/ VLSI Design/ or related discipline with good academic record. Further the candidate having the knowledge of Microelectronics and VLSI CAD tools (Cadence Virtuoso, Mentor Graphics, Synopsys, Siemens EDA Tools), Analog IC Design, MATLAB, C++, UNIX and relevant areas with GATE score will also be preferable.
Application send via email to js_ubhi@yahoo.com
For more details related to eligibility criteria, fee, pattern, annexure, place of posting etc. refer to the attachments below.