Principal Scientist and 2 Other Post in IITG via Walk-In-Interview
Event Status : Created Event
Timeline
Important Dates
Date of Interview | 08/09/2023, 09/09/2023, 10/09/2023 |
Application Closing Date | 05/09/2023 |
Application Opening Date | 26/08/2023 |
Other Important Information
Appointment Type | Walk-In-Interview |
Application Submission Method | Online |
Qualification Required | Doctorate, Postgraduate, Graduate |
Total Vacancies | 20 |
Location of Posting/Admission | Kamrup Metropolitan District, Assam, India, 781034 |
Post Type | Contractual |
Interview | Yes |
Work Experience | Yes |
Organisation Type | Educational Institution |
Website | https://www.iitg.ac.in/ |
Place of Posting/Admission | Guwahati, Assam, India |
Salary | 148750, 89750, 67330 |
Department/Subject | Electronics and Electrical Engineering |
Application Link | https://forms.gle/PGc5AwFm7qjraGhG8, https://forms.gle/53mu225BAfjc4ZVWA, https://forms.gle/SaMYjM8WWPLSy9VeA |
Note: This information is common for all posts. For details on specific posts, refer to the official notification.
Posts Released
Important Updates
Refer to the official notification for more details.
Application Summary
Indian Institute of Technology Guwahati invites application from eligible candidates for Walk-in-Interview for the following posts:
Post Name: Principal Scientist
Essential Qualification:
(1) PhD in EC/EE/CS with 3 years of relevant experience or
(2) MTech/ME in VLSI/ Microelectronics/ CS with 6 Years of relevant experience or
(3) BTech/BE in EC/EE/CS with 8 years relevant experience. Candidates having the knowledge of chip signoff/tape-out and the commercial EDA tools and the VLSI Design flow are preferred.
Post Name: Senior Project Engineer
Essential Qualification:
(1) Ph. D in EC/EE/CS or
(2) MTech/ME in VLSI/ Microelectronics/CS with 4 Years of relevant experience or
(3) BTech/BE in EC/EE/CS with 6 years relevant experience. Candidates having the knowledge of chip signoff/tape-out and the commercial EDA tools and the VLSI Design flow are preferred.
(3) BTech/BE in EC/EE/CS with 6 years relevant experience. Candidates having the knowledge of chip signoff/ tape -out and the commercial EDA tools and the VLSI Design flow are preferred.
Post Name: Project Scientist - 1
Essential Qualification:
PhD in VLSI/ Microelectronics/ CS, or MTech/ME in VLSI/ Microelectronics/CS with 2 Years of relevant experience or
(2) BTech/BE in EC/EE/CS with 4 years relevant experience. Candidates having the knowledge of chip signoff/tape-out and the commercial EDA tools and the VLSI Design flow are preferred
Place of Interview: EEE Conference Room or EEE Meeting Room
For more details related to eligibility criteria, fee, pattern, annexures, place of posting etc. refer to the attachments below.