Project Engineer Post in CDAC via Walk-in-Interview
Event Status : Created Event
Timeline
Important Dates
Application Closing Date | 12/10/2023 |
Application Opening Date | 29/09/2023 |
Other Important Information
Appointment Type | Walk-In-Interview |
Application Submission Method | Online |
Age Limit | 18-32 |
Qualification Required | Graduate, Postgraduate |
Total Vacancies | 8 |
Advertisement Number | CDACT/RCT/09/2023 |
Location of Posting/Admission | Thiruvananthapuram District, Kerala, India, 695572 |
Salary | 37500 |
Post Code | CDACT/PE/01 |
Post Type | Contractual |
Interview | Yes |
Place of Posting/Admission | Thiruvananthapuram, Kerala, India |
Age Relaxation Type | SC/ST, Other Backward Class, Person with Benchmark Disabilities |
Quota/Reservation | Scheduled Castes, Scheduled Tribes, Other Backward Classes, Ex-servicemen, Economically Weaker Sections, PWBD Quota |
Organisation Type | Non-Educational Institution |
Website | https://www.cdac.in/ |
Application Link | https://docs.google.com/forms/d/e/1FAIpQLSdQHfGFOow3JS9ID1TOv6Syw_wDiKvPAaUMHsVYaLYPq4VQFA/viewform |
Note: This information is common for all posts. For details on specific posts, refer to the official notification.
Posts Released
Important Updates
Refer to the official notification for more details.
Application Summary
Centre for Development of Advanced Computing invites application from eligible candidates for Walk-in-Interview for the following posts:
Post Name: Project Engineer
Essential Qualification:
First class (60% or equivalent CGPA) B.E/ B. Tech. in Electronics/ Electronics and Communication Engineering OR
First class (60% or equivalent CGPA) Post Graduate degree in Electronics OR
M Tech in Electronics/VLSI & Embedded Systems Design
Desirable: ASIC Physical Design: Synthesis, Floor planning, Power planning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis & Physical Verification. ASIC Design in 40nm/ advanced process nodes. Expertise in Cadence / Synopsys lC design flows & scripting using TCL, Perl, etc. Processor Design: RISC-V or other processor lSAs, micro-architecture and digital logic design, computer architecture, hardware description languages viz. Verilog or Bluespec SystemVerilog or VHDL, FPGA design, programming skills in C, C++, or Python.
Place of Interview: CDAC, Vellayambalam, Thiruvananthapuram
For more details related to eligibility criteria, fee, pattern, annexures, place of posting etc. refer to the attachments below.