Project Engineer Post in CDAC via Walk-in-Interview
Event Status : Created Event
Timeline
Event Information
Centre for Development of Advanced Computing invites application from eligible candidates for Walk-in-Interview for the following posts:
Post Name: Project Engineer
Essential Qualification:
First class (60% or equivalent CGPA) B.E/ B. Tech. in Electronics/ Electronics and Communication Engineering OR
First class (60% or equivalent CGPA) Post Graduate degree in Electronics OR
M Tech in Electronics/VLSI & Embedded Systems Design
Desirable: ASIC Physical Design: Synthesis, Floor planning, Power planning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis & Physical Verification. ASIC Design in 40nm/ advanced process nodes. Expertise in Cadence / Synopsys lC design flows & scripting using TCL, Perl, etc. Processor Design: RISC-V or other processor lSAs, micro-architecture and digital logic design, computer architecture, hardware description languages viz. Verilog or Bluespec SystemVerilog or VHDL, FPGA design, programming skills in C, C++, or Python.
Place of Interview: CDAC, Vellayambalam, Thiruvananthapuram
For more details related to eligibility criteria, fee, pattern, annexures, place of posting etc. refer to the attachments below.
Attachments
Important Dates
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Start Date | 29/09/2023 |
Last date | 12/10/2023 |
Recruitment Details
Post Wise Details
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Post Name | Project Engineer |
Recruitment Type | Walk-In-Interview |
Post Code | CDACT/PE/01 |
Post Type | Contractual |
Educational Qualification | Graduation, Postgraduation |
Salary | 37500 |
Apply/Application Details
Job History
Status | Description | Date | |
---|---|---|---|
Created Event Project Engineer Post in CDAC via Walk-in-Interview | Project Engineer Post in CDAC via Walk-in-Interview | 07/10/2023 |