Junior Research Fellow Post in DYSL-QT via Direct Recruitment
Event Status : Created Event
Timeline
Important Dates
Application Closing Date | 30/07/2023 |
Application Opening Date | 01/07/2023 |
Other Important Information
Appointment Type | Direct Recruitment, Research Fellowship |
Application Submission Method | Composite |
Age Limit | 18-27 |
Qualification Required | Graduate, Postgraduate |
Total Vacancies | 3 |
Location of Posting/Admission | Pune District, Maharashtra, India, 412219 |
Exam | CSIR NET, GATE, UGC NET |
Salary | 31000 |
Post Type | Contractual |
Place of Posting/Admission | Pune, Maharashtra, India |
Age Relaxation Type | SC/ST, Other Backward Class |
Interview | Yes |
Work Experience | Yes |
Organisation Type | Non-Educational Institution |
Website | https://www.drdo.gov.in/labs-and-establishments/drdo-young-scientist-laboratory-dysl-qt |
Application Link | https://www.drdo.gov.in/labs-and-establishments/drdo-young-scientist-laboratory-dysl-qt |
Note: This information is common for all posts. For details on specific posts, refer to the official notification.
Posts Released
Important Updates
Refer to the official notification for more details.
Application Summary
Defence Research and Development Organisation Young Scientist Lab Quantum Technologies invites applications for the following posts via direct recruitment:
Post Name: Junior Research Fellow
Essential Qualification:
B.E/B.Tech Degree in Electro-nics and Communication Engineering/ Electronics/ Electrical and Electronics/Electronics and Telecommunication in 1st Division with valid NET/GATE qualification (OR) M.E/M.Tech Degree in Electro-nics and Communication/Electro-nics/Electrical and Electronics/Electronics and Telecommuni-cation Engineering in 1st Division both at Graduate and Postgraduate level.
Desirable:
1. Verilog coding, experience of working with FPGA specially ZYNQ architecture.
2. Hands-on-experience working on FPGAs, bare-metal programming. Linux level programming
3. Experience in Verilog/ VHDL based programming, high speed communication interfaces like gigabit transceivers, Ethemet etc., error correction protocols and its implementation on FPGA.
4. C, Python based program-ming, MATLAB.
5. Proficiency in Communi- cation and DSP algorithms.
6. Having knowledge of working in embedded system and FPGA based design.
7. Exposure to Quantum Technologies
Address to send the application: The Candidate must fill in the application form and send it to the Director, DRDO Young Scientist Laboratory- Quantum Technology Defence Research and Development Organisation (DRDO) Hall No 1, Ground Floor, Vigyan Upakendra DIAT Campus, Girinagar, Pune-411025, Maharashtra along with relevant documents.
Application can also be sent via email to director@dysl-qt.drdo.in
For more details related to eligibility criteria, fee, pattern, annexure, place of posting etc. refer to the attachments below.