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  • Junior Research Fellow Post in DRDO via Direct Recruitment

    Event Status : Created Event

Timeline

Important Dates

Application Closing Date
17/06/2023
Application Opening Date
19/05/2023

Other Important Information

Appointment Type
Direct Recruitment, Research Fellowship, Examination
Application Submission Method
Offline, Online
Age Limit
18-27
Qualification Required
Graduate, Postgraduate
Total Vacancies
3
Location of Posting/Admission
Pune District, Maharashtra, India, 412219
Exam
CSIR NET, GATE, UGC NET
Post Type
Contractual
Place of Posting/Admission
Pune, Maharashtra, India
Age Relaxation Type
SC/ST, Other Backward Class
Work Experience
Yes
Organisation Type
Non-Educational Institution
Website
https://www.drdo.gov.in/

Note: This information is common for all posts. For details on specific posts, refer to the official notification.

Posts Released

1. Junior Research Fellow

Important Updates

Refer to the official notification for more details.

Application Summary

Defence Research and Development Organisation has released a notification for the Junior Research Fellow post. Interested candidates can apply from 19/05/2023 to 17/06/2023. Download the official notification for details on eligibility, post information, job procedure, pay scale, and more.

Defence Research and Development Organisation invites applications for the following posts via direct recruitment:

Post Name: Junior Research Fellow

Essential Qualification: B.E/B.Tech Degree in Electronics Communication Engineering / Electronics/Electrical and Electronics/Electronics and Telecommunication in IST Division with Valid NET/GATE qualification (OR) ME/MTech Degree in Electronics Communication Electronics/Electrical and Electronics/Electronics and Telecommunication Engineering in IST Division both at Graduate and Postgraduate level.

Desirable:

  • Verilog coding, experience of working with FPGA specially ZYNQ architecture.

  • Hands-on-experience working on FPGAs, bare-metal programming, Linux level programming.

  • Experience in Verilog/ VHDL based programming, high speed communication interfaces like gigabit transceivers, Ethernet etc., error correction protocols and its implementation on FPGA.

  • C, Python based programming, MATLAB.

  • Proficiency in Communication and DSP algorithms.

  • Having knowledge of working in embedded system and FPGA based design.

  • Exposure to Quantum Technologies

Address to send the application: The Candidate must fill in the application form and send it to the Director, DRDO Young Scientist Laboratory-Quantum Technology Defence Research and Development Organisation (DRDO) Hall No-1, Ground Floor,Vigyan Upakendra, DIAT Campus, Girinagar, Pune-411025, Maharashtra along with relevant documents.

Application can also be sent via email to dyslqtdrdo@gmail.com

For more details related to eligibility criteria, fee, pattern, annexure, place of posting etc. refer to the attachments below.