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  • Junior Research Fellow Post in DRDO via Direct Recruitment

    Event Status : Created Event

Timeline

Important Dates

Application Closing Date
10/06/2023
Application Opening Date
12/05/2023

Other Important Information

Appointment Type
Direct Recruitment
Application Submission Method
Offline, Online
Age Limit
18-27
Qualification Required
Graduate, Postgraduate
Total Vacancies
3
Location of Posting/Admission
Pune District, Maharashtra, India, 412219
Exam
CSIR NET, GATE, UGC NET
Salary
31000
Place of Posting/Admission
Pune, Maharashtra 411001, India
Age Relaxation Type
SC/ST, Other Backward Class
Interview
Yes
Work Experience
Yes
Organisation Type
Non-Educational Institution
Website
https://www.drdo.gov.in/

Note: This information is common for all posts. For details on specific posts, refer to the official notification.

Posts Released

1. Junior Research Fellow

Important Updates

Refer to the official notification for more details.

Application Summary

Defence Research and Development Organisation has released a notification for the Junior Research Fellow post. Interested candidates can apply from 12/05/2023 to 10/06/2023. Download the official notification for details on eligibility, post information, job procedure, pay scale, and more.

Defence Research and Development Organisation invites applications for the following posts via direct recruitment:

Post Name: Junior Research Fellow

Essential Qualification:

  1. B.E/B.Tech Degree in Electronics & Communication Engg Electronics/Electrical & Electronics/Electronics & Telecommunication in 1st Division with Valid NET/GATE qualification OR

  2. ME/M.Tech Degree in Electronics & Communication / Electronics/Electrical Electronics/Electronics Telecommunication Engg in 1st Division both at Graduate and Postgraduate level

Desirable:

  1. Verilog coding, experience of working with FPGA specially ZYNQ architecture.

  2. Hands-on-experience working on FPGAs, Bare-metal Programming, Linux level Programming

  3. Experience in Verilog/ VHDL based programming, high speed communication interfaces like gigabit transceivers, Ethernet etc., error correction protocols and its implementation on FPGA.

  4. C, Python based programming, MATLAB.

  5. Proficiency in Communication and DSP algorithms

  6. Having knowledge of working in embedded system and FPGA based design

  7. Exposure to Technologies Quantum

Address to send the application: The Candidate must fill in the application form and send it to The Director, DRDO Young Scientist Laboratory- Quantum Technology Defence Research and Development Organisaiton (DRDO) Hall No. 1, Ground Floor, Vigyan Upakendra, DIAT Campus, Girinagar, Pune-411025, Maharashtra along with relevant documents.

Application can also be sent via email to director@dyslqt.drdo.in

For more details related to eligibility criteria, fee, pattern, annexure, place of posting etc. refer to the attachments below.