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  • Junior Research Fellow Post in NIT Delhi via Direct Recruitment

    Event Status : Created Event

Timeline

Important Dates

Application Closing Date
05/05/2024
Application Opening Date
05/04/2024

Other Important Information

Appointment Type
Direct Recruitment, Research Fellowship
Application Submission Method
Online
Age Limit
18-32
Qualification Required
Graduate, Postgraduate
Total Vacancies
1
Location of Posting/Admission
New Delhi, Delhi, India, 110011
Age Relaxation Type
SC/ST, Other Backward Class, Person with Benchmark Disabilities
Post Type
Contractual
Work Experience
Yes
Organisation Type
Educational Institution
Website
https://nitdelhi.ac.in/
Place of Posting/Admission
New Delhi, Delhi, India
Salary
37000
Interview
Yes
Application Link
https://docs.google.com/forms/d/1y4lGX_n5Il49Bh1Ohng6iiS4WrwR2nP_3Z35m5LnRI0/prefill

Note: This information is common for all posts. For details on specific posts, refer to the official notification.

Posts Released

1. Junior Research Fellow

Important Updates

Refer to the official notification for more details.

Application Summary

National Institute of Technology Delhi has released a notification for the Junior Research Fellow post. Interested candidates can apply from 05/04/2024 to 05/05/2024. Download the official notification for details on eligibility, post information, job procedure, pay scale, and more.

National Institute of Technology Delhi invites applications for the following posts via direct recruitment:

Post Name: Junior Research Fellow

Essential Qualification:

  • Candidates with a Bachelor’s degree in Engineering/Technology in Electronics and Communication Engineering or Electrical and Electronics Engineering or Computer Science and Engineering or other relevant discipline. and

  • Master’s degree in Engineering/Technology in the fields of VLSI Design/ Microelectronics/Embedded Design/ECE or other relevant discipline, with a minimum of 60% aggregate marks (or) CGPA of 6.5/10 in UG or PG for JRF under GEN/EWS/OBC category and 55% aggregate marks or equivalent CGPA of 6.0 for SC/ST candidates

Desirable: Knowledge in Verilog HDL, Cadence Tool, Siemens EDA Tools (Mentor graphics), Synopsys TCAD etc.

For more details related to eligibility criteria, fee, pattern, annexure, place of posting etc. refer to the attachments below.